Portfolio · Rev 2026.10
Ivan Huang
ECE Master's student at Cornell specializing in CPU logic design: front-end RTL and microarchitecture. Below are the projects I've built across the stack, from transistor layout to autonomous robots.
| Program | M.Eng, Electrical & Computer Eng. '26 |
|---|---|
| Prior | B.S., Electrical & Computer Eng. '26 |
| School | Cornell University · Ithaca, NY |
| Focus | CPU logic design · RTL · μarch |
| Projects | 18 in 5 areas, each with a live demo |
| Updated | Oct 2026 |
Projects
Each figure is a live simulation of how the project works. Open Details for the approach, results and original figures.
About
I'm an Electrical and Computer Engineering Master's student at Cornell, specializing in CPU logic design: front-end RTL and microarchitecture.
More broadly I'm interested in computer architecture, ASIC/FPGA design and integrated circuits, and the projects above reflect that range: full-custom CMOS layout, a self-written RTL-to-GDS flow, multicore RISC-V, FPGA and HLS accelerators, firmware and robotics.
Education
| 2026 | M.Eng, Electrical & Computer EngineeringCornell University · Jan – Dec 2026 |
|---|---|
| 2026 | B.S., Electrical & Computer EngineeringCornell University · Aug 2022 – May 2026 · GPA 3.81 |
Tools & methods
Contact
Open to connecting about CPU logic design, RTL and microarchitecture, computer architecture and ASIC/FPGA roles.
| qh229@cornell.edu | |
| linkedin.com/in/ivan-huang-4a02a7246 ↗ | |
| GitHub | github.com/IvannnHuang ↗ |